[sv-ac] RE: 1698 sampled value functions - review

Hi Ed,

 

See my comments below.

 

Lisa

 

________________________________

From: Eduard Cerny [mailto:Eduard.Cerny@synopsys.com] 
Sent: Tuesday, January 22, 2008 2:30 PM
To: Lisa Piper; Eduard Cerny
Cc: sv-ac@eda.org
Subject: RE: 1698 sampled value functions - review

 

Hi Lisa, John,

 

I think that the proposal is ready  for  a vote. 

 

Still, I wonder about the following statement:

 

Since synthesized code executes in the active region, the past_variable
is used directly. Provided that

the model follows synthesis rules and is race-free, the behavior should
be equivalent to that in the original

model using $past. The other functions, $rose, $fell and $stable follow.

[Lisa Piper >>>] I agree with you. I had incorporated what was written
in the original Mantis item. Does it work to simply strike this sentence
out?

 

Can we really talk about "synthesis rules" Which ones? The LRM does not
introduce it. Similarly in the restrictions on always blocks, can we say


procedure that meets the requirements for modeling synthesizable
sequential logic behavior ?

[Lisa Piper >>>] I used the same text as was already in 9.2.2.4

9.2.2.4 Sequential logic always_ff procedure

The SystemVerilog always_ff procedure can be used to model synthesizable
sequential logic behavior.

For example:

always_ff @(posedge clock iff reset == 0 or posedge reset) begin

r1 <= reset ? 0 : r2 + 1;

...

Finally, "default clock" should be perhaps changed to "default
clocking".

[Lisa Piper >>>] no problem

 

Best regards,

ed

 

	
________________________________


	From: Lisa Piper [mailto:piper@cadence.com] 
	Sent: Tuesday, January 22, 2008 10:22 AM
	To: Eduard Cerny
	Cc: sv-ac@eda.org
	Subject: 1698 sampled value functions

	<<1698_sampled_value_functions_08_1_22.pdf>> 

	Hi Ed,

	I have incorporated your suggestions.

	Lisa


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