RE: [sv-ac] call to vote on 2088

Hi Dimitry,

Are you saying that even the action blocks or subroutine calls in
checkers will not have this method ?

I think the postponed region sampling will not work well for continuous
check bits. In the checker proposal it says that continuous assignment
is executed at every time step. But if you consider the following two
examples:

assign a = s.ended;
Vs.
assign a = s.triggered;

As per the current LRM, the .ended remains true only in Observed region.
So, by the time postponed region comes the value of 'a' would be 0
always. Whereas the value of .triggered remains true throughout the
simulation time step so in postponed region, the value of 'a' would be 1
in the time step endpoint passes.

But the 1900 proposal says that there is no difference in using .ended
or .triggered in continuous assignments (as there is assumption that the
checker variables are read only in Observed region).

Thanks.
Manisha

-----Original Message-----
From: Korchemny, Dmitry [mailto:dmitry.korchemny@intel.com] 
Sent: Tuesday, January 22, 2008 4:34 PM
To: Fais Yaniv; Kulshrestha, Manisha; Havlicek John; sv-ac@eda.org
Subject: RE: [sv-ac] call to vote on 2088

Hi Yaniv,

I don't think that the sample() method may be called in the checker
according to 2088. Probably it needs be stated more explicitly in the
proposal.

Regards,
Dmitry

-----Original Message-----
From: Fais Yaniv [mailto:yaniv.fais@freescale.com] 
Sent: Tuesday, January 22, 2008 12:56 PM
To: Korchemny, Dmitry; Kulshrestha, Manisha; Havlicek John;
sv-ac@eda.org
Subject: RE: [sv-ac] call to vote on 2088

 
Hi Dmitry,

covergroup sampling can be done also using the build in .sample()
method, this can be activated from assertion code also.

since both assertions and checker variables are calculated in the
Observed region, what is the value seen by a .sample() called within
concurrent assertion code which looks at a checker variable ?


Yaniv

-----Original Message-----
From: owner-sv-ac@eda.org [mailto:owner-sv-ac@eda.org] On Behalf Of
Korchemny, Dmitry
Sent: Tuesday, January 22, 2008 09:36
To: Kulshrestha, Manisha; Havlicek John; sv-ac@eda.org
Subject: RE: [sv-ac] call to vote on 2088

Hi Manisha,

As far as I understand this proposal defines a reasonable behavior of
covergroups.

There are two options of sampling covergroups: at the change of the
clock and in the Postponed region, depending on the value of strobe
variable. In case of the Postponed value sampling there should be no
difference between the regular variables and checker variables - the new
values of the variables are used.

Consider the case of immediate sampling on the example from the
proposal:

covergroup cg_active @(posedge clk);
cp_active : coverpoint active
{
	bins idle = { 1'b0 };
	bins active = { 1'b1 };
}
cp_active_d1 : coverpoint active_d1
{
	bins idle = { 1'b0 };
	bins active = { 1'b0 };
}
endgroup

Suppose that active is a continuous bit. It will be sampled in the
Active region here, before the clock change, i.e., the old value of
active will be used. The same situation happens in case of the well
formed RTL: the value of the variable assigned continuously should
change after the clock rise only.

active_d1 is a sequential bit, and it also changes in the Observed
region, therefore in the Active region the old value of the variable
active_d1 will be used. The same situation happens in RTL when the
variable is assigned in a nonblocking assignment - the old value is
taken in the covergroup.

Do you agree?

Thanks,
Dmitry

-----Original Message-----
From: owner-sv-ac@server.eda.org [mailto:owner-sv-ac@server.eda.org] On
Behalf Of Kulshrestha, Manisha
Sent: Tuesday, January 22, 2008 8:02 AM
To: john.havlicek@freescale.com; sv-ac@server.eda.org
Subject: RE: [sv-ac] call to vote on 2088

Hi,

I vote 'no' as I am not sure if this proposal handles all the sampling
issues related to covergroups. I am not completely familiar with
covergroups but I do see that in the LRM there are multiple ways to
sample the variables which are used in covergroups. The 1900 also talks
about sampling of checker variables. E.g. in 16.18.6.2 it says:


Sequential check bits (see 16.8.5.1) are sampled in the Preponed region,
as the regular variables are. Continuous check bits (see 16.18.6.1) are
never sampled either in assignments (see 16.18.6.1) or in concurrent
assertions.

What will happen if these check bits are used in covergroups ? The new
proposal does not talk about it.

Thanks.
Manisha

-----Original Message-----
From: owner-sv-ac@server.eda.org [mailto:owner-sv-ac@server.eda.org] On
Behalf Of John Havlicek
Sent: Wednesday, January 16, 2008 7:23 AM
To: sv-ac@server.eda.org
Subject: [sv-ac] call to vote on 2088

Hi Folks:

This is the call to vote on the revised proposal for Mantis 2088.

The document on Mantis is 

   2008_covergroups_20080114.pdf

Please vote if you are eligible.  See the details below.

J.H.

------------------------------------------------------------------------
----------
Ballot on Mantis 2088

- Called on 2008-01-15, final ballots due by 2008-01-21 T 23:59-08:00.

 v[xxxxxxxxxxxxxxxxxxxxx-xxxxxxxxxxxxxxxxxxxxxxxx-xx] Doron Bustan
(Intel)
 v[xxxxx--xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx-x] Eduard Cerny
(Synopsys)     
 n[----------------------x-xxx---------x-x-xxx-x---x] Surrendra Dudani
(Synopsys)
 v[xxxxxxxx-xxxxxx-xxxxxxxxx-xx-xxxxx-xxx-xxx-------] Yaniv Fais
(Freescale)
 t[xxxx--xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx] John Havlicek
(Freescale - Chair)
v[xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxrxxxxxxxxxxxxx-xxx] Dmitry Korchemny
(Intel - Co-Chair)  v[xxxxx-xxxxxxxxx-xxx-x--xx--xxxxx----------xx-xxxx]
Manisha Kulshrestha (Mentor Graphics)
n[------------------------------xxxxx-------x-xx-x-] Jiang Long (Mentor
Graphics)
 n[---------x------------x--xxx.....................] Joseph Lu (Altera)
v[xxxxxxxxxxxxxxxxxxx..............................] Johan Martensson
(Jasper)
 n[---------------------------x--x-xx--xx-xxxxxxx-x-] Hillel Miller
(Freescale)
 v[xxxxx-xxxx-xxxxxxxxxxxxxxxxxxx-xxxxxxxx-xxxxxxxxx] Lisa Piper
(Cadence)
 v[xxxxxx-x-x-xx-xxxxxxx-x-xxxxx-x..................] Erik Seligman
(Intel)
 n[-------x-x----x--------xxxx-----xxxx-xx----------] Tej Singh (Mentor
Graphics)
 v[xxxxxx-x-xxxxxx--xxxxxxxx-xxxxxxxxxxxxxxxxxxxxxxx] Bassam Tabbara
(Synopsys)
 v[xxxxxxxxx-xxxxxxxxxxxxx-xxxxxxxxxx...............] Tom Thatcher (Sun
Microsystems)
   |------------------------------------------------- attendance on
2008-01-15
 |--------------------------------------------------- voting eligibility
for this ballot
|---------------------------------------------------- email ballots
received

        Legend:
                x = attended
                - = missed
                r = represented
                . = not yet a member
                v = valid voter (2 out of last 3 or 3/4 overall)
                n = not a valid voter
                t = chair eligible to vote only to make or break a tie

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