RE: [sv-ac] New version of proposal for 2110 (checkers in loops) posted

Hi Dmitry--

Here's another draft.  Tell me what you think.


-----Original Message-----
From: Korchemny, Dmitry 
Sent: Monday, January 21, 2008 1:05 AM
To: Seligman, Erik
Cc: Bustan, Doron; Eduard Cerny; Surrendra.Dudani@synopsys.COM;
Bresticker, Shalom
Subject: RE: [sv-ac] New version of proposal for 2110 (checkers in
loops) posted

And one more comment. In the checker proposal it is written now that the
automatic variables cannot be passed to a checker. This proposal (2110)
should relax these limitations when a checker is called in a loop.

Thanks,
Dmitry

-----Original Message-----
From: owner-sv-ac@server.eda.org [mailto:owner-sv-ac@server.eda.org] On
Behalf Of Seligman, Erik
Sent: Thursday, January 17, 2008 7:23 PM
To: john.havlicek@freescale.com; sv-ac@server.eda.org
Subject: [sv-ac] New version of proposal for 2110 (checkers in loops)
posted


I made some corrections to the examples, based on issues Ed pointed out:
 	http://www.verilog.org/mantis/view.php?id=2110

John-- I think we should add this to our working list to discuss at
upcoming meetings.  Thanks!

Dmitry-- it might be useful for you to start looking at it & make
initial comments.  This first version is very closely based on 1995, but
I'm not sure if something more is needed for the checkers case.

 

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