RE: [sv-ac] inferred conditions

So in your opinion, it is legal to put the concurrent assertion in the
procedural code regardless.  I think this will make debug more
difficult, but perhaps that is ok.   Are there other opinions?  

 

Lisa

 

________________________________

From: Eduard Cerny [mailto:Eduard.Cerny@synopsys.com] 
Sent: Friday, January 11, 2008 9:35 AM
To: Lisa Piper; sv-ac@eda.org
Subject: RE: [sv-ac] inferred conditions

 

Hi Lisa,

 

as far as I understand it, if there is no if/case, then there is no
enabling condition. For clocks, if there is no default clocking then it
is an error.

 

ed

 

	 

	
________________________________


	From: owner-sv-ac@eda.org [mailto:owner-sv-ac@eda.org] On Behalf
Of Lisa Piper
	Sent: Thursday, January 10, 2008 6:35 PM
	To: sv-ac@eda.org
	Subject: [sv-ac] inferred conditions

	What should happen if I can't infer an enabling condition or
clock, for example:

	always @(posedge mclk) begin

	case (a)

	 1: begin

	  @(negedge clk)

	  b <= c;

	  r4_p: assert property (r4);

	 end

	 default: d <= c;

	endcase

	end

	Is this an error if I have defined a default clock?  In other
words, am I not allowed to have this or does it simply mean that I can't
infer the clock and enabling condition?  In 1737, we have only shown
'nice' cases.  

	lisa

	
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