[sv-ac] inferred conditions

What should happen if I can't infer an enabling condition or clock, for
example:

		always @(posedge mclk) begin
		case (a)
		 1: begin
		  @(negedge clk)
		  b <= c;
		  r4_p: assert property (r4);
		 end
		 default: d <= c;
		endcase
		end

Is this an error if I have defined a default clock?  In other words, am
I not allowed to have this or does it simply mean that I can't infer the
clock and enabling condition?  In 1737, we have only shown 'nice' cases.


lisa

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