RE: [sv-ac] call to vote on 1900

Hi Manisha,

 

The reference scheduling algorithm is explained in detail in 16.18.5.4.
The reference algorithm is not event-based, it only says that at each
simulation step the values of all continuous checker variables are
reevaluated in their dependency order. The implementation may choose to
reevaluate the assignments only when their right-hand side changes.

 

Thanks,

Dmitry

 

________________________________

From: owner-sv-ac@server.eda.org [mailto:owner-sv-ac@server.eda.org] On
Behalf Of Kulshrestha, Manisha
Sent: Wednesday, December 19, 2007 11:06 AM
To: Korchemny, Dmitry; Bresticker, Shalom; sv-ac@server.eda.org
Subject: RE: [sv-ac] call to vote on 1900

 

Hi Dimitry,

 

I think even assignment at every simulation time step Is not enough if
dependencies are not considered. So it should be clearly mentioned that
the assignments will be done based on dependencies (.i.e. whenever right
hand side changes).

 

Thanks.

Manisha

 

From: owner-sv-ac@server.eda.org [mailto:owner-sv-ac@server.eda.org] On
Behalf Of Korchemny, Dmitry
Sent: Wednesday, December 19, 2007 2:03 PM
To: Bresticker, Shalom; sv-ac@server.eda.org
Subject: RE: [sv-ac] call to vote on 1900

 

Shalom,

 

But there is no user-visible effect of this optimization. From the user
point of view the assignment to checker variables is made at each
simulation step consistently with their dependency order.

 

Thanks,

Dmitry

 

________________________________

From: Bresticker, Shalom 
Sent: Wednesday, December 19, 2007 10:29 AM
To: Korchemny, Dmitry; 'sv-ac@server.eda.org'
Subject: RE: [sv-ac] call to vote on 1900

 

But that is the point. One has to understand what are the user-visible
effects. Doron did not understand the user-visible effect of his
optimization. Others won't either.

 

Shalom

	 

	
________________________________


	From: Korchemny, Dmitry 
	Sent: Wednesday, December 19, 2007 10:20 AM
	To: Bresticker, Shalom; 'sv-ac@server.eda.org'
	Subject: RE: [sv-ac] call to vote on 1900

	Hi Shalom,

	 

	The simulation semantics is explained in detail in 16.18.5.4.
The implementer is always free to make any optimizations consistent with
the description.

	 

	In 4.3 it is explicitly written:

	"Within the following

	event execution model definitions, there is a great deal of
choice, and differences in some details of execution

	are to be expected between different simulators. In addition,
SystemVerilog simulators are free to use

	different algorithms from those described in this clause,
provided the user-visible effect is consistent with

	the reference algorithm."

	 

	Thanks,

	Dmitry

	 

	-----Original Message-----
	From: Bresticker, Shalom 
	Sent: Wednesday, December 19, 2007 10:14 AM
	To: Korchemny, Dmitry; sv-ac@server.eda.org
	Subject: RE: [sv-ac] call to vote on 1900

	 

	If that is what you mean, then maybe that is what you should
say. Otherwise, an implementor may have to be afraid that there is
another reason, which he is not aware of, why the LRM says to execute at
every time step.

	 

	Shalom

	 

	> I think that the statement that the continuous assignment of 

	> checker variables shall execute at every time step is clearer 

	> than the explanation about topological sorting (this is 

	> explained in the subclause describing the simulation 

	> semantics). Essentially, this definition is a matter of 

	> phrasing only, and the implementation may be event-driven, it 

	> should just take the topological sort into account.

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