RE: [sv-ac] Support of two-dimensional interface instantiation?

We already answered it in SV-BC.

Shalom 

> -----Original Message-----
> From: owner-sv-ac@server.eda.org 
> [mailto:owner-sv-ac@server.eda.org] On Behalf Of Korchemny, Dmitry
> Sent: Sunday, December 02, 2007 9:29 AM
> To: sv-ac@server.eda.org
> Subject: [sv-ac] Support of two-dimensional interface instantiation?
> 
> This e-mail was bounced by the server. Forwarding it to SV-AC.
> 
> Dmitry
> 
> -----Original Message-----
> 
> Hi,
> 
> In 1800-2005, it only supports two-dimensional interface 
> instantiation.
> Will 1800-2008 support two-dimensional interface instantiation?
> This feature is very commonly used to model array processor 
> and FPGA architectures in which a system is composed of many 
> similar building blocks. Each building block is identified by 
> two indexes.
> 
> For example,
> 
>     Interface array_cup_bus (input a, inout b, input clk);
>       Inout data;
>       Input r_w;
>     endinterface: array_cup_bus
> 
>     module cup (array_cup_bus cup_bus);
>     endmodule
> 
>     module mem (array_cup_bus cup_bus);
> 
>     endmoudle
> 
>     module array_cup (input a, inout b, input clk);
> 
>        array_cup_bus cup_bus [1:3][1:3] (a, b, clk);
>        cpu cpu1(cpu_bus[1][1]);
>        mem mem1(cpu_bus[1][1]);
>        cpu cpu1(cpu_bus[1][2]);
>        mem mem1(cpu_bus[1][2]);
>        cpu cpu1(cpu_bus[1][3]);
>        mem mem1(cpu_bus[1][3]);
>     endmoudle
> 
> 
> Thanks,
> 
> Joseph Lu, Ph.D.
> IC Design & Verification Manager
> Altera Corp.
> 101 Innovation Dr.
> San Jose, CA95134
> Tel:408-5448694
> Email:jlu@altera.com
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