[sv-ac] 1900 (checkers) and variables types keywords

Hi,
 
In the current proposal inside checkers all the variables are defined
using the keyword "freevar".
 
It seems to me however that those variables can be differentiated into 3
main categories:
1. non deterministic variables
2. (deterministic) state variables
3. (deterministic) continuous assigned variables
 
I think that giving the same keyword for all those types is confusing
since it makes it difficult to read and understand which variables are
non-deterministic and which aren't (you have to look for all the
assignments and check that a variable isn't assigned anywhere) therefore
I suggest using different keywords for those different types.
 
The first type (non deterministic state variables) can retain the name
"freevar" whereas for the other two I suggest the existing names of
"var" for state variables and "wire" for continuous assigned variables.
 
The semantic should remain the same as in the current proposal only that
the names of those different types should change.
 
variables of type "wire" can only participate in "assign" only (not
always_check assignments).
variables of type "var" can have initial value assignment and be
assigned inside "always_check" using one nonblocking assignment.
 
variables of type wire or var can be assigned freevars,
for example:
checker ck(integer inp1);
  freevar integer f;
  wire integer d = f + inp1;
...
 
"d" is still considered deterministic since it simply has the value of
"f" + "inp1", "inp1" in this case can a deterministic signal coming from
another module (sampled) or another freevar from another checker,"f"
however is free (under assumptions).
 
a freevar therefore doesn't participate in always_check assignments but
only in assumptions.
 
There is an issue with uninitialized variables,
for example:
var [3:0] counter;
always_check @clk
  counter <= counter+1;
The above variable has a nondeterministic initial value inside
checkers,I think it should be considered "var" and not "freevar" however
since its next state function is given.
 
Another issue is that wires can have only 4 state typed variables in
modules, I don't think this is needed inside checkers so if someone
finds it confusing to remove this limitation inside checkers I suggest
using only "assign" instead of "wire",e.g: "assign integer d = f + inp1;
" so the declaration and continuous assignment are in the same line.
 
 
What do other people think of this suggested change ? is this worth
changing or am I the only one finding the usage of "freevar" for all
types confusing ?
 
 
Yaniv
 
 
 

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