RE: [sv-ac] inconsistency in "default clocking" terminology

Yes, I also noticed that. I understood that as if there is a concept
called "default clocking", to which all references refer, and then there
is a specification statement that defines what the default clocking for
the given design entity is, which is explained in 14.12. So, indeed now
everything looks quite consistent. The only inconsistency was in the
14.12 itself.

 

Thanks,

            Yulik.

 

________________________________

From: owner-sv-ac@server.eda.org [mailto:owner-sv-ac@server.eda.org] On
Behalf Of Lisa Piper
Sent: Monday, November 19, 2007 4:30 PM
To: Feldman, Yulik; sv-ac@server.eda.org
Subject: RE: [sv-ac] inconsistency in "default clocking" terminology

 

Yulik,

 

By the way, I did a search of the rest of the document and there are a
lot of references to "default clocking" but not to the syntax statement,
so I think we are consistent.  It would not hurt to double check me on
this Yulik.

 

Lisa

 

________________________________

From: Feldman, Yulik [mailto:yulik.feldman@intel.com] 
Sent: Monday, November 19, 2007 9:02 AM
To: Lisa Piper; sv-ac@eda.org
Subject: RE: [sv-ac] inconsistency in "default clocking" terminology

 

Yes, it looks good. Though I personally liked the "specification
statement" more than just "specification", since this specification is
indeed a statement.

 

--Yulik.

 

________________________________

From: Lisa Piper [mailto:piper@cadence.com] 
Sent: Monday, November 19, 2007 3:52 PM
To: Feldman, Yulik; sv-ac@eda.org
Subject: RE: [sv-ac] inconsistency in "default clocking" terminology

 

1648 is already fixing this section so I added this to that proposal.
Please confirm that the following addresses your concern and I will
upload the proposal to Mantis.

 

Lisa

=====================

 

14.12 Default clocking

REPLACE in Syntax 14-3-Default clocking syntax

 

The syntax for the default cycle specification statement is as follows:

 

module_or_generate_item_declaration ::= // from A.1.4
              ...
            | default clocking clocking_identifier ;

WITH

The syntax for default clocking specification the default cycle
specification statement is as follows:

 

module_or_generate_item_declaration ::= // from A.1.4

         ...
            | default clocking clocking_identifier ; ;

         ...

[Note to the Editor:  There are two changes in the syntax itself.  One
is to change the font of the terminating semicolon from non-bold black
to bold red.  The other is to add the ellipsis (...) at the end to
represent the omission of "default disable iff", which is not relevant
in this context.] 

 

 

________________________________

From: owner-sv-ac@eda.org [mailto:owner-sv-ac@eda.org] On Behalf Of
Feldman, Yulik
Sent: Monday, November 19, 2007 5:09 AM
To: sv-ac@eda.org
Subject: [sv-ac] inconsistency in "default clocking" terminology

 

FYI,

 

In 1800/D4, 14.12 "Default clocking", the "default clocking" is referred
to once as "default cycle specification statement" and once as "default
clocking specification". The terminology should be consistent. The
"cycle" is a clear typo, but there should also be consistency in whether
it is a "specification statement" or just a "specification".

 

--Yulik.

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