RE: [sv-ac] sampled assertion function vs data types - refereing to prior simulation

From: danielm <danielm_at_.....>
Date: Thu Nov 15 2007 - 02:44:29 PST
exactly what about nets?
 what should happened if i've assertions like below:
 
reg clk;
wire w;
reg r;
assign w=r
initial begin
    clk=1;
.....
end
z:assert property(@(posedge clk) w===1'bz));
x:assert property(@(posedge clk) w===1'bx));
 
Which from above should fail?
 
DANiel
  _____  

From: owner-sv-ac@server.eda.org [mailto:owner-sv-ac@server.eda.org] On
Behalf Of Bresticker, Shalom
Sent: Thursday, November 15, 2007 10:43 AM
To: Korchemny, Dmitry; sv-ac@server.eda-stds.org
Subject: RE: [sv-ac] sampled assertion function vs data types - refereing to
prior simulation


There are other types of data types besides variables. E.g., nets.
 
Shalom


  _____  

From: owner-sv-ac@server.eda.org [mailto:owner-sv-ac@server.eda.org] On
Behalf Of Korchemny, Dmitry
Sent: Thursday, November 15, 2007 11:34 AM
To: danielm; sv-ac@server.eda-stds.org
Subject: RE: [sv-ac] sampled assertion function vs data types - refereing to
prior simulation



Hi Daniel,

 

D4 draft contains the following definition in 16.8.3:

 

" The value of an expression sampled in the Preponed region corresponding to
time 0 is the result of evaluating

the expression using the initial values of the variables comprising the
expression. The initial value of a

static variable is the value assigned in its declaration, or, in the absence
of such an assignment, it is the

default (or uninitialized) value of the corresponding type (see 6.7, Table
6-1). The initial value of any other

variable or signal is the default value of the corresponding type (see 6.7,
Table 6-1). For example, if $sampled(

y) is called at time 0, and y is of type logic, the value returned is X."

 

A similar definition is provided for other sampled value functions.

 

Regards,

Dmitry


  _____  


From: owner-sv-ac@server.eda.org [mailto:owner-sv-ac@server.eda.org] On
Behalf Of danielm
Sent: Thursday, November 15, 2007 11:28 AM
To: sv-ac@server.eda-stds.org
Subject: [sv-ac] sampled assertion function vs data types - refereing to
prior simulation

 

Chapter 17.7.3 describes that value of sampled function (sampled, past,
stable) in time 0 should be equal X.

 

Is it so for all types of variables?

For reg it is ok.

What about bit, wire, enum etc....

 

 

DANiel

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Received on Thu Nov 15 02:44:57 2007

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