RE: [sv-ac] sampled assertion function vs data types - refereing to prior simulation

Hi Daniel,

 

D4 draft contains the following definition in 16.8.3:

 

" The value of an expression sampled in the Preponed region
corresponding to time 0 is the result of evaluating

the expression using the initial values of the variables comprising the
expression. The initial value of a

static variable is the value assigned in its declaration, or, in the
absence of such an assignment, it is the

default (or uninitialized) value of the corresponding type (see 6.7,
Table 6-1). The initial value of any other

variable or signal is the default value of the corresponding type (see
6.7, Table 6-1). For example, if $sampled(

y) is called at time 0, and y is of type logic, the value returned is
X."

 

A similar definition is provided for other sampled value functions.

 

Regards,

Dmitry

________________________________

From: owner-sv-ac@server.eda.org [mailto:owner-sv-ac@server.eda.org] On
Behalf Of danielm
Sent: Thursday, November 15, 2007 11:28 AM
To: sv-ac@server.eda-stds.org
Subject: [sv-ac] sampled assertion function vs data types - refereing to
prior simulation

 

Chapter 17.7.3 describes that value of sampled function (sampled, past,
stable) in time 0 should be equal X.

 

Is it so for all types of variables?

For reg it is ok.

What about bit, wire, enum etc....

 

 

DANiel


-- 
This message has been scanned for viruses and 
dangerous content by MailScanner <http://www.mailscanner.info/> , and is

believed to be clean. 
---------------------------------------------------------------------
Intel Israel (74) Limited

This e-mail and any attachments may contain confidential material for
the sole use of the intended recipient(s). Any review or distribution
by others is strictly prohibited. If you are not the intended
recipient, please contact the sender and delete all copies.

-- 
This message has been scanned for viruses and
dangerous content by MailScanner, and is
believed to be clean.