RE: [sv-ac] 1737 Enabling Condition proposal updated

From: Lisa Piper <piper_at_.....>
Date: Fri Sep 28 2007 - 18:50:47 PDT
Hi Tom and Ed,

Here is the revised version with your changes incorporated. I've
converted the purple to all blue (ab).  I have a copy with the purple to
distinguish changes since the last vote if someone wants it.

lisa

-----Original Message-----
From: Thomas.Thatcher@Sun.COM [mailto:Thomas.Thatcher@Sun.COM] 
Sent: Friday, September 28, 2007 4:32 PM
To: Eduard Cerny
Cc: Lisa Piper; sv-ac@eda-stds.org
Subject: Re: [sv-ac] 1737 Enabling Condition proposal updated

Hi Ed,

Yes, It does mention 4-valued logic -- at the end of the example on the
next
page.  It took me a while to figure out that it wasn't the same example
repeated.  That's why I think it would be better to introduce the
example
before it appears so people know why it it included.

Thanks,

Tom

Eduard Cerny wrote On 09/28/07 11:54 AM,:
> Hi Tom,
> 
> I think that the 2nd example does mention 4-valued logic.
> ed 
> 
> 
>>-----Original Message-----
>>From: owner-sv-ac@eda.org [mailto:owner-sv-ac@eda.org] On 
>>Behalf Of Thomas Thatcher
>>Sent: Friday, September 28, 2007 2:27 PM
>>To: Lisa Piper
>>Cc: sv-ac@eda-stds.org
>>Subject: Re: [sv-ac] 1737 Enabling Condition proposal updated
>>
>>Hi Lisa,
>>
>>I have reviewed 1737:  Here are my comments:
>>
>>	1.  p 3:   "consider the affect"  should be "consider 
>>the effect"
>>				 ^^^^^^
>>
>>	2.  Do you have the same example in twice?
>>		p 4: "As another example, for simplicity, 
>>assume that . . ."
>>		This third example is identical to the first example.
>>
>>		Oh, I see: the third example uses 4-state 
>>variables, while
>>		first example used 2-state variables.
>>		
>>		Perhaps you can add a note right up front to 
>>explain why the
>>		almost identical example appears again.
>>
>>		Change:
>>			"As another example, for simplicity, assume"
>>		To:
>>			"Four-state variables in 
>>if/if-else/if-else-if/ or
>>			case/casex/casez conditions require 
>>special handling.
>>			If the bit variables in the previous 
>>examples are
>>			replaced with a logic variables, the assertions
>>			embedded in the else clause require different
>>			semantics.
>>
>>		Also, in this example do you want a to be 
>>logic[1:0], or do
>>		you want a single bit.  It shouldn't matter to 
>>the example.
>>
>>
>>Tom
>>
>>
>>Lisa Piper wrote On 09/28/07 09:59 AM,:
>>
>>> <<1737_070928_enablingCondition.pdf>>
>>>
>>>Hi all,
>>>
>>>I have completed the updates requested by the champions for Mantis
>>>1737.  My changes are in purple. All purple will change to 
>>
>>blue for the
>>
>>>final review. Ed has reviewed the changes. It would good to have a
>>>second or third reviewer before another vote is re-called.  Thanks!
>>>
>>>Lisa
>>>
>>>
>>>-- 
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>>
>>-- 
>>------------------
>>Thomas J. Thatcher
>>Sun Microsystems
>>------------------
>>
>>-- 
>>This message has been scanned for viruses and
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>>

-- 
------------------
Thomas J. Thatcher
Sun Microsystems
------------------

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Received on Fri Sep 28 18:51:15 2007

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