RE: [sv-ac] 1737 Enabling Condition proposal updated

Hi Tom,

I think that the 2nd example does mention 4-valued logic.
ed 

> -----Original Message-----
> From: owner-sv-ac@eda.org [mailto:owner-sv-ac@eda.org] On 
> Behalf Of Thomas Thatcher
> Sent: Friday, September 28, 2007 2:27 PM
> To: Lisa Piper
> Cc: sv-ac@eda-stds.org
> Subject: Re: [sv-ac] 1737 Enabling Condition proposal updated
> 
> Hi Lisa,
> 
> I have reviewed 1737:  Here are my comments:
> 
> 	1.  p 3:   "consider the affect"  should be "consider 
> the effect"
> 				 ^^^^^^
> 
> 	2.  Do you have the same example in twice?
> 		p 4: "As another example, for simplicity, 
> assume that . . ."
> 		This third example is identical to the first example.
> 
> 		Oh, I see: the third example uses 4-state 
> variables, while
> 		first example used 2-state variables.
> 		
> 		Perhaps you can add a note right up front to 
> explain why the
> 		almost identical example appears again.
> 
> 		Change:
> 			"As another example, for simplicity, assume"
> 		To:
> 			"Four-state variables in 
> if/if-else/if-else-if/ or
> 			case/casex/casez conditions require 
> special handling.
> 			If the bit variables in the previous 
> examples are
> 			replaced with a logic variables, the assertions
> 			embedded in the else clause require different
> 			semantics.
> 
> 		Also, in this example do you want a to be 
> logic[1:0], or do
> 		you want a single bit.  It shouldn't matter to 
> the example.
> 
> 
> Tom
> 
> 
> Lisa Piper wrote On 09/28/07 09:59 AM,:
> >  <<1737_070928_enablingCondition.pdf>>
> > 
> > Hi all,
> > 
> > I have completed the updates requested by the champions for Mantis
> > 1737.  My changes are in purple. All purple will change to 
> blue for the
> > final review. Ed has reviewed the changes. It would good to have a
> > second or third reviewer before another vote is re-called.  Thanks!
> > 
> > Lisa
> > 
> > 
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> ------------------
> Thomas J. Thatcher
> Sun Microsystems
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