RE: [sv-ac] 2005

I would use the same mechanism as for assertions with no clock:

 

"If the assertion appears in a context with no defined

clock, it shall be treated as if clocked by a virtual clocking event
that is triggered at the beginning of every

time step."

 

Doron

 

________________________________

From: Korchemny, Dmitry 
Sent: Sunday, September 16, 2007 4:34 PM
To: Bustan, Doron; Seligman, Erik; sv-ac@server.eda-stds.org
Subject: RE: [sv-ac] 2005

 

Hi Doron,

 

But how would you infer the clock for the following invocation?

 

module m(input clk1, clk2, i1, i2);

wire b = test_1(i1, i2);

endmodule

 

Thanks,

Dmitry

 

________________________________

From: owner-sv-ac@server.eda.org [mailto:owner-sv-ac@server.eda.org] On
Behalf Of Bustan, Doron
Sent: Sunday, September 16, 2007 2:43 PM
To: Seligman, Erik; sv-ac@server.eda-stds.org
Subject: [sv-ac] 2005

 

Hi Erik,

 

I have a question about assertions in functions:

Let's look at the example below:

 

------------------------------------------------------------------------
--

module m(input clk1, clk2, i1, i2);

bit b;

 

function automatic bit test_1(bit x, y);

   test_1  = (x == y);

  a1: assert property (@(posedge clk1) x == y);

endfunction

 

always @ (posedge clk2) b <= test_1(i1, i2);

 

endmodule

------------------------------------------------------------------------
--

 

The assertion a1 is clocked on "posedge clk1" but the function is called
on "posedge clk2".

Since there is no "ref" on the function's port list, the arguments
values are passed by value.

This means, that a1 "see" the values of "i1, i2" on "posedge clk2". It
that your intent?

It looks like the clocking event in the assertion is misleading. Maybe
we should restrict the 

Clocking event to be inferred from the context of the function call?

 

Doron

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