RE: [sv-ac] 2005

Doron,
 
What do you mean by "see" ?
 
In fact, the whole meaning of a clocked concurrent assertion in an
automatic function is not clear to me. Is this described somewhere?
 
Regards,
Shalom


________________________________

	From: owner-sv-ac@server.eda.org
[mailto:owner-sv-ac@server.eda.org] On Behalf Of Bustan, Doron
	Sent: Sunday, September 16, 2007 2:43 PM
	To: Seligman, Erik; sv-ac@server.eda-stds.org
	Subject: [sv-ac] 2005
	
	

	Hi Erik,

	 

	I have a question about assertions in functions:

	Let's look at the example below:

	 

	
------------------------------------------------------------------------
--

	module m(input clk1, clk2, i1, i2);

	bit b;

	 

	function automatic bit test_1(bit x, y);

	   test_1  = (x == y);

	  a1: assert property (@(posedge clk1) x == y);

	endfunction

	 

	always @ (posedge clk2) b <= test_1(i1, i2);

	 

	endmodule

	
------------------------------------------------------------------------
--

	 

	The assertion a1 is clocked on "posedge clk1" but the function
is called on "posedge clk2".

	Since there is no "ref" on the function's port list, the
arguments values are passed by value.

	This means, that a1 "see" the values of "i1, i2" on "posedge
clk2". It that your intent?

	It looks like the clocking event in the assertion is misleading.
Maybe we should restrict the 

	Clocking event to be inferred from the context of the function
call?

	 

	Doron

	
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