RE: [sv-ac] immediate assertions in always_comb

Doron,

> begin
>   a = b; 
>   assert (a ==c)
> end
>  
> is similar  to
>  
> always @(b) 
> begin
>   a = b;
>   assert (a == c)
> end
>
> [...] It would have been more intuitive if c was
> added to the sensitivity list as well.


I'm not quite sure why you omitted 'c' from 
the second block's event control.  Surely
always_comb constructs its "sensitivity list"
from *every* net and variable that participates 
in an expression (with some exceptions, as listed
in 9.2.2.2.1); and "a==c" in your assert is 
just an expression?  And we can reliably assume
that the value of 'a' cannot change except by 
execution of the always_comb, since it is forbidden
to write to a variable from anywhere else if it
is written from within an always_comb.

There is another issue: always_comb processes
execute once from top to bottom at time zero,
which the alternative form would not necessarily
do.  To mimic always_comb in that respect, it's
necessary to put the @(b,c) just before the "end":

  always begin
    a = b;
    assert (a==c);
    @(b,c);
  end

Please excuse me if I've missed your point.
--
Jonathan Bromley, Consultant

DOULOS - Developing Design Know-how
VHDL * Verilog * SystemC * e * Perl * Tcl/Tk * Project Services

Doulos Ltd. Church Hatch, 22 Market Place, Ringwood, Hampshire, BH24 1AW, UK
Tel: +44 (0)1425 471223                   Email: jonathan.bromley@doulos.com
Fax: +44 (0)1425 471573                           Web: http://www.doulos.com

The contents of this message may contain personal views which
are not the views of Doulos Ltd., unless specifically stated.

-- 
This message has been scanned for viruses and
dangerous content by MailScanner, and is
believed to be clean.