Hi all, John and I have modified the proposal and resubmitted it. There is one minor change in the body of the proposal: instead of the term "design", the term "the entire elaborated SystemVerilog model" is used throughout the proposal. In the preamble, the feedback on champions' notes has been added (this is a slightly modified version of the feedback draft I sent for the last meeting, and we briefly discussed it in the meeting). If you have a chance, please, review this feedback before today's meeting so that we could discuss it today. I am attaching the latest version of the proposal for convenience. Thanks, Dmitry -- This message has been scanned for viruses and dangerous content by MailScanner, and is believed to be clean.
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