[sv-ac] New proposal (2005) on solution for glitches in immediate assertions

Hi all--

As you may have noticed, I just posted one more proposal:
        http://www.verilog.org/mantis/view.php?id=2005
The associated doc is attached to this email as well for convenience.

I think this is a pretty important one, a solution for the glitch issue
in immediate assertions, but it will require a bit of discussion.  We
have been wavering on whether to propose this as an extension of
concurrent assertions (which is what we did in the current doc), or as a
new type of assertion altogether, 'final assertions', that are similar
to immediate assertions but use the shadow-variable methodology
described in the doc to avoid glitches.

As an extension to concurrent assertions, this proposal may be
controversial, since it actually changes their semantics in certain
situations in a non-backwards-compatible way. (Example in the doc.) On
the other hand, we're not sure if proposing a new type of assertion
would be even more controversial.

If you have some spare time to take a look & comment, we would be
interested to hear your views.

John-- it would also be nice to get this on the meeting agenda.

Thanks!




 


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