RE: [sv-ac] Checker construct proposal: any comments yet?

Just a note that Mantis 1619 is a proposed enhancement to all default
values on module (and presumably program and interface) input ports.

Shalom
 

> -----Original Message-----
> From: owner-sv-ac@server.eda.org 
> [mailto:owner-sv-ac@server.eda.org] On Behalf Of Brad Pierce
> Sent: Monday, July 02, 2007 7:06 PM
> To: sv-ac@server.eda-stds.org
> Subject: Re: [sv-ac] Checker construct proposal: any comments yet?
> 
> Erik,
> 
> An enhancement proposal will usually get more feedback if it 
> is also distributed on the reflector, instead of just 
> uploaded to Mantis, so I've attached a copy of your current version.
> 
> Your document is not in the form of a formal proposal, but 
> apparently it would add new keywords 'checker' and 
> 'endchecker', plus a new system function $notdet() for making 
> a nondeterminstic choice between arguments.
> 
> Is a system function the best syntax for the latter 
> capability?  Why not add a true operator like |~| for internal choice?
> 
> Also, I don't think it would be a good idea to add comments 
> like the following to the LRM
> 
>   "A free variable appears only in checkers, and thus should 
> never be synthesized into silicon."
> 
> -- Brad
> 
> -----Original Message-----
> From: owner-sv-ac@eda.org [mailto:owner-sv-ac@eda.org] On 
> Behalf Of Seligman, Erik
> Sent: Monday, July 02, 2007 8:17 AM
> To: sv-ac@eda-stds.org
> Subject: [sv-ac] Checker construct proposal: any comments yet?
> 
> 
> Hi all--
> 
> Just wanted to send a reminder to take a look at this new 
> proposal, on 'checker' constructs, when you get the chance:
> 	http://www.verilog.org/mantis/view.php?id=1900
> 
> This is a relatively major language enhancement, so it might 
> be good to start discussion going so we can begin revising it 
> & converge in a reasonable time frame.  I suspect there will 
> be many questions and issues.
> 
> Thanks!
> 
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