RE: [sv-ac] call to vote on Mantis 1361

Since the cross-reference in 19.10 has been created by the editor of
draft3a. We can ask the editor to make it more precise (20.7.1.2 instead
of 20.7). Or do we need another mantis for this ?

Manisha

-----Original Message-----
From: Bresticker, Shalom [mailto:shalom.bresticker@intel.com] 
Sent: Wednesday, July 25, 2007 2:08 PM
To: Bresticker, Shalom; Kulshrestha, Manisha;
john.havlicek@freescale.com; sv-ac@server.eda-stds.org
Subject: RE: [sv-ac] call to vote on Mantis 1361

But both sections should use the more precise cross-reference that
appears in the 1361 proposal.

Shalom  

> -----Original Message-----
> From: Bresticker, Shalom 
> Sent: Wednesday, July 25, 2007 11:37 AM
> To: 'Kulshrestha, Manisha'; john.havlicek@freescale.com; 
> sv-ac@server.eda-stds.org
> Subject: RE: [sv-ac] call to vote on Mantis 1361
> 
> When I wrote "consistent", I meant "same". I agree that the 
> meaning was already the same.
> 
> Thanks,
> Shalom 
> 
> > -----Original Message-----
> > From: Kulshrestha, Manisha [mailto:Manisha_Kulshrestha@mentor.com]
> > Sent: Wednesday, July 25, 2007 11:35 AM
> > To: Bresticker, Shalom; john.havlicek@freescale.com; 
> > sv-ac@server.eda-stds.org
> > Subject: RE: [sv-ac] call to vote on Mantis 1361
> > 
> > Hi shalom,
> > 
> > The wording in the 19.10 is already consistent with it in 
> draft3a. So, 
> > I'll make the wording same as 19.10 in this new section.
> > 
> > Manisha
> > 
> > -----Original Message-----
> > From: owner-sv-ac@server.eda.org
> > [mailto:owner-sv-ac@server.eda.org] On Behalf Of Bresticker, Shalom
> > Sent: Wednesday, July 25, 2007 12:54 PM
> > To: john.havlicek@freescale.com; sv-ac@server.eda-stds.org
> > Subject: RE: [sv-ac] call to vote on Mantis 1361
> > 
> > If this is going to be the wording in a new 19.11, the 
> wording of the 
> > corresponding paragraph in 19.10 should be consistent with it.
> > 
> > Thanks,
> > Shalom
> >  
> > 
> > > - Change
> > > 
> > >      When the system task is specified with arguments, the first
> > >      argument indicates levels of the hierarchy, 
> consistent with the
> > >      corresponding argument to the Verilog $dumpvars system
> > >      task. Subsequent arguments specify which scopes of 
> the model to
> > >      control. These arguments can specify entire scopes (module,
> > >      program, interface, always block or initial block) or
> > individual
> > >      assertions. Please refer to 20.7.1.2 for the definition of
> > >      $dumpvars.
> > > 
> > >   to
> > > 
> > >      When the system task is specified with arguments, the first
> > >      argument indicates levels of the hierarchy, 
> consistent with the
> > >      corresponding argument to the $dumpvars system task (see
> > >      20.7.1.2). Subsequent arguments specify which scopes
> > of the model
> > >      to control. These arguments can specify entire 
> scopes (module,
> > >      program, interface, always block or initial block) or
> > individual
> > >      assertions.
> > 
> > --
> > This message has been scanned for viruses and dangerous content by 
> > MailScanner, and is believed to be clean.
> > 

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