RE: [sv-ac] review 1681

Hello Doron,

1. It is the intent to allow clock changes inside always block, i.e.,
the assertion clock dominates over always block clock dominates over
default clocking.

2. I think it is a recommendation. Dmitry?

Best regards,
ed
 

> -----Original Message-----
> From: owner-sv-ac@eda.org [mailto:owner-sv-ac@eda.org] On 
> Behalf Of Doron Bustan
> Sent: Wednesday, May 09, 2007 11:35 AM
> To: sv-ac@eda.org
> Subject: [sv-ac] review 1681
> 
> here are my (minor) comments
> 
> 1. in 17.7.3 (inferred clock) the change in the wording implies
>     precedence of a clock in an assertion over a clock inferred from
>     an initial/always block. In 17.13.5 it says that if both clocking 
> events
>     exist, they should be the same. There is no strict 
> contradiction here,
>     but I think it is misleading.
> 
> 2. At the beginning of p6, it is not clear to me whether the alignment
>     off the clock to the global clock is a requirement (with 
> elab error 
> when violated,)
>     or a recommendation.
> 
> Doron
> 
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