RE: [sv-ac] Question on clock flow

I agree that it was hard to figure out.  Can we think of it as though
the clock can only change after a "##1" or "|=>".  This would imply that
it cannot change after an "and" or "or" or other sequence operator.  In
16.13.1, it states:  "Multiclocked sequences are built by concatenating
singly clocked subsequences using the single-delay concatenation
operator ##1."  And later it states: "Differently clocked or
multiclocked sequence operands cannot be combined with any sequence
operators
other than ##1."  

Perhaps we can add something in the precedence table of 16-24?  In this
section we have not introduced multi-clk yet but ...

Lisa 

-----Original Message-----
From: owner-sv-ac@eda.org [mailto:owner-sv-ac@eda.org] On Behalf Of John
Havlicek
Sent: Friday, May 11, 2007 10:06 AM
To: Eduard.Cerny@synopsys.com
Cc: sv-ac@eda-stds.org
Subject: Re: [sv-ac] Question on clock flow

Hi Ed:

My interpretation is (B).  You will get (A) from

   @c (@d x) and y

J.H.

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> Hi,
> 
> What is your interpretation of the clock flow in the LRM on the 
> following example:
> 
> Question here to answer is what does @c (@d x and y) mean? A or B ?
> ------------------------------------
> (A) (@d x) and (@c y)
> (B) (@d x) and (@d y)
> 
> -------
> 
> Thanks,
> 
> ed
> 
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