> Would it be appropriate to say that if (b) P1 else P2 needs to be > defined as (bit'b |-> P1) and (!(bit'b) |->P2)? I don't think so. That would give you the least significant bit of b, which (I think) is not the intent. Generally, any "boolean" condition b in Verilog can be rewritten as (b!=0). Sometimes I prefer to use the reduction operator (|b) but this doesn't work for "real" values, only for integral values. So I would much prefer to see (bit'(b!=0) |-> P1) and (!(bit'(b!=0)) |->P2) However, the bit'() cast does indeed collapse unknown (x,z) values to false (0) and I agree it is more elegant than my formulation using !==0. -- Jonathan Bromley, Consultant DOULOS - Developing Design Know-how VHDL * Verilog * SystemC * e * Perl * Tcl/Tk * Project Services Doulos Ltd. Church Hatch, 22 Market Place, Ringwood, Hampshire, BH24 1AW, UK Tel: +44 (0)1425 471223 Email: jonathan.bromley@doulos.com Fax: +44 (0)1425 471573 Web: http://www.doulos.com The contents of this message may contain personal views which are not the views of Doulos Ltd., unless specifically stated. -- This message has been scanned for viruses and dangerous content by MailScanner, and is believed to be clean.Received on Sun Apr 22 08:06:21 2007
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