RE: [sv-ac] "if else" definition needs corrections - mantis 1786

> "if (b) P1 else P2" is defined in annex E as a shortcut to
> "(b |-> P1) and (!b |-> P2)". The problem with this definition
> is that b = X, neither P1 nor P2 are required to hold. This is
> inconsistent with SV procedural "if else" where the else block
> should be executed.
>
>  I enter a mantis item 1786.
> 
> A simple correction that will fix that is to define "if (b) 
> P1 else P2"
> as a shortcut to "((b ===1) |-> P1) and ((b!==1) |-> P2)".
> 
> But with this definition, "if (b) P1 else P2" is not equivalent to
> "if (!b) P2 else P1", so I am not sure what do we need.

I don't think there is anything you can do about this. 
Unknown conditionals in the bifurcating "if...else" have
always been handled like this in Verilog...

  if (b) P1 else P2;  ===>  if (b) P1 else P2 maybe P2;

and if you invert the test, of course you get

  if (!b) P2 else P1 maybe P1;

which is not exactly the same.  Since we cannot specify the
"maybe" branch explicitly in a single "if" clause, it seems 
to me that there is no way out of this.

Note that your "b===1" formulation is correct only if b
is a single bit.  It might be preferable to say

  ( ((b!=0)===1) |-> P1 ) and ( ((b!=0)!==1) |-> P2 ).

(Or is this in a context where b is known to be only
one bit wide?  If so, apologies for the irrelevance.)
-- 
Jonathan Bromley, Consultant

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