Re: [sv-ac] call to vote on Mantis 1737

> Has "verification statement" been defined somewhere?

According to 17.13 in IEEE Std 1800-2005 --

A property on its own is never evaluated for checking an expression. It
must be used within a verification statement for this to occur. A
verification statement states the verification function to be performed
on the property. The statement can be one of the following:

    - assert to specify the property as a checker to ensure that the
property holds for the design
    - assume to specify the property as an assumption for the
environment
    - cover to monitor the property evaluation for coverage 

-- Brad

[ In reply to http://www.eda-stds.org/sv-ac/hm/3804.html . ]

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