RE: [sv-ac] call to vote on Mantis 1466

Hi Dave,

I understand and share your concern about the proposed shortcuts. Since
I am trying to keep neutrality here, I want to provide one more reason
in their favor: sequences ARE regular expressions, and there is a
commonly used syntax for regular expressions: *, +, ?. I personally am
used to this notation both from scripting languages and from other
property specification languages. I suggest discussing this enhancement
in today's meeting.

Thanks,
Dmitry
 
-----Original Message-----
From: Rich, Dave [mailto:Dave_Rich@mentor.com] 
Sent: Tuesday, March 27, 2007 2:45 AM
To: Korchemny, Dmitry; Bassam Tabbara; john.havlicek@freescale.com;
sv-ac@server.eda-stds.org
Subject: RE: [sv-ac] call to vote on Mantis 1466

Dmitry,

I agree that shortcuts, up to some point, make the code easier to read.
At the same time, shortcuts make the language more complex and harder to
learn, especially when they are not consistently applied throughout the
language.

If I were a more prolific writer, I could fill pages on why I think the
implicit/context arguments are not the right thing to do. If someone had
spent the appropriate amount of time defining all of the formal argument
types needed for properties/sequences in the first place, we wouldn't
need mantis 1601 as a band-aid. Giving the user too many ways to do the
same things makes the language unmanageable.

Dave


> -----Original Message-----
> From: owner-sv-ac@server.eda.org [mailto:owner-sv-ac@server.eda.org]
On
> Behalf Of Korchemny, Dmitry
> Sent: Sunday, March 25, 2007 5:27 AM
> To: Bassam Tabbara; john.havlicek@freescale.com;
sv-ac@server.eda-stds.org
> Subject: RE: [sv-ac] call to vote on Mantis 1466
> 
> Hi Bassam,
> 
> I don't see a problem "?" have a different meaning in Verilog. We have
> many precedents of Verilog keyword reuse. The last one was your
> suggestion about reusing "context" keyword to indicate an "implicit"
> type:) I understand your concern about mistaken use of [*]. The reason
> to introduce shortcuts is clarity and readability only, SVA is
sometimes
> difficult to read. We may think about other shortcuts, which would be
> more readable and not error prone, e.g.,
> 
> a.+ instead of a[*1:$], a.* instead of a[*0:$], and a.? instead of
> a[*0:1].
> 
> E.g.,
> 
> a[*0:$] ##1 b |=> c[*0:1] ##1 d
> 
> will become
> 
> a.* ##1 b |=> c.? ##1 d
> 
> This is not a complete syntax proposal, I chose the syntax for
> illustration purposes only.
> 
> Thanks,
> Dmitry
> 
> -----Original Message-----
> From: owner-sv-ac@server.eda.org [mailto:owner-sv-ac@server.eda.org]
On
> Behalf Of Bassam Tabbara
> Sent: Friday, March 23, 2007 6:12 AM
> To: john.havlicek@freescale.com; sv-ac@server.eda-stds.org
> Subject: RE: [sv-ac] call to vote on Mantis 1466
> 
> I vote no.
> 
> I have reservations about the ROI of the syntax sugaring here. "?" has
a
> different meaning in Verilog. As for the [*], if a user say made a
> mistake and dropped a digit from [*2] say, they get a nasty [*0:$]
> eating up their time, a couple of extra characters for clarity seem
well
> worth it.
> 
> Thx.
> -Bassam.
> 
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