RE: [sv-ac] an example for discussion of 1668

Hi John,

Why cannot the user write these properties as:

   property q(logic sig);
	 logic v;
       (sig, v = !sig) |-> sig_b ##1 v;
   endproperty

   assert property (
      @(ev1) sig_a |=> @(ev2) q(sig_b)
   );
?

Thanks,
Dmitry

-----Original Message-----
From: owner-sv-ac@server.eda.org [mailto:owner-sv-ac@server.eda.org] On
Behalf Of John Havlicek
Sent: Monday, March 26, 2007 6:57 PM
To: sv-ac@server.eda-stds.org
Subject: [sv-ac] an example for discussion of 1668

Hi Dmitry:

I had an action item to send you an example to help
us discuss the problem of local variable initialization
when the clock is changing and a signal is being assigned
to the local variable in the initialization.

Here is an example that I think covers this situation:

   property q(input local logic v);
       (v, v = !v) |-> sig_b ##1 v;
   endproperty

   assert property (
      @(ev1) sig_a |=> @(ev2) q(sig_b)
   );

J.H.

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