RE: [sv-ac] call to vote on Mantis 1466

Hi Bassam,

I don't see a problem "?" have a different meaning in Verilog. We have
many precedents of Verilog keyword reuse. The last one was your
suggestion about reusing "context" keyword to indicate an "implicit"
type:) I understand your concern about mistaken use of [*]. The reason
to introduce shortcuts is clarity and readability only, SVA is sometimes
difficult to read. We may think about other shortcuts, which would be
more readable and not error prone, e.g.,

a.+ instead of a[*1:$], a.* instead of a[*0:$], and a.? instead of
a[*0:1]. 

E.g., 

a[*0:$] ##1 b |=> c[*0:1] ##1 d

will become

a.* ##1 b |=> c.? ##1 d

This is not a complete syntax proposal, I chose the syntax for
illustration purposes only.

Thanks,
Dmitry

-----Original Message-----
From: owner-sv-ac@server.eda.org [mailto:owner-sv-ac@server.eda.org] On
Behalf Of Bassam Tabbara
Sent: Friday, March 23, 2007 6:12 AM
To: john.havlicek@freescale.com; sv-ac@server.eda-stds.org
Subject: RE: [sv-ac] call to vote on Mantis 1466

I vote no.

I have reservations about the ROI of the syntax sugaring here. "?" has a
different meaning in Verilog. As for the [*], if a user say made a
mistake and dropped a digit from [*2] say, they get a nasty [*0:$]
eating up their time, a couple of extra characters for clarity seem well
worth it.

Thx.
-Bassam.

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