RE: [sv-ac] 1728

Hi John,

Please, see my comments below.

Thanks,
Dmitry

-----Original Message-----
From: owner-sv-ac@server.eda.org [mailto:owner-sv-ac@server.eda.org] On
Behalf Of John Havlicek
Sent: Wednesday, March 14, 2007 9:40 PM
To: sv-ac@server.eda-stds.org
Subject: [sv-ac] 1728

Hi Ed:

I read the first few pages of the 1728 proposal and became
confused.  Maybe you can help clarify.

Below are my notes and questions.

J.H.

----------------------------

p. 1, item 5.  Why do variables in the declarative scope of "let" that
   are referenced globally have to be declared before being referenced?
   Does this rule already apply to other global references to such 
   variables?  Is it essential or a convenience?

[Korchemny, Dmitry] This should be similar to sequences and properties.
The LRM reads: "Variables used in a sequence that are not formal
arguments to the sequence are resolved according to the scoping rules
from the scope in which the sequence is declared." How do you interpret
this statement? Does it mean that the variable referenced by a sequence
must be defined before this sequence?

p. 2, item 9.  I don't understand it.

[Korchemny, Dmitry] Consider the following example:

logic b, c, d, clk;
let a = b && c;
let ap = $past(a);
assert property(@(posedge clk) ap == a && !d);

Though a is not a model signal, its value may be reported by the
debugger for user convenience. ap cannot be considered as a debug signal
because its clock is inferred during the instantiation only, and
different istantiation of ap may have different values.

This item may be removed from the proposal, because it describes an
implementation detail.

p. 2, items 14,15.  Are these appropriate for the standard?

[Korchemny, Dmitry] These should be dropped, of course.

Question:  Why can't "sequence" declarations be used instead of "let"?

[Korchemny, Dmitry] Here is an example:

let bits_high(sig, n) = $countones(sig) == n;
assert (rst || bits_high(a, 3));

You cannot use a sequence here.
           
Question:  Can the syntax of "let" be aligned with sequence/property 
  constructs?

[Korchemny, Dmitry] It can, of course, but it will be verbose. For user
point of view the concise syntax is better. There are other SV
constructs having similar syntax, e.g., alias.

Question:  p. 3, example 1).  Are the hierarchical paths m.a, m.b 
  correct?  What if module m is instantiated rather than top-level?

[Korchemny, Dmitry] As far as I understand, they are. It is legal to
specify either an instance name of a module name in the hierarchy.

p. 3, example 2).  This example should show the scoping effect of 
  the redeclaration of x. 
[Korchemny, Dmitry] I am not sure I understand this comment.

 The ability to place the "let" as a statement
  in a procedural scope seems to differentiate it from other
declarations.

[Korchemny, Dmitry] It is different, indeed. The rationale behind it is
to define things locally or to refer directly to the variables defined
within this block. The same problem exists for sequences and properties.
I suggest consider the usefulness question for all these constructs
together.
`
p. 4, example 3).  What kind of begin-end block is this?  A generate
block?
  I'm having trouble parsing this given that it encloses declarations.

[Korchemny, Dmitry] Is a generate statement missing here (if, for)?

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