RE: [sv-ac] SV-AC proposals

Ed,

The summary description you gave to 1756 is,
"The LRM does indicate how the control tasks $asserton, $assertoff and
$assertkill affect the behavior of verification statements".

I did not understand that.
Did you mean "does not" instead of "does"?

Thanks,
Shalom

> -----Original Message-----
> From: owner-sv-ac@server.eda.org [mailto:owner-sv-ac@server.eda.org]
> On Behalf Of Eduard Cerny
> Sent: Monday, March 12, 2007 11:40 PM
> To: sv-ac@server.eda-stds.org
> Cc: Eduard Cerny
> Subject: [sv-ac] SV-AC proposals
> 
> Hello,
> 
> I have created a new Mantis entry #1756 (behavior of assertions in
> initial block when $asserton/off/kill are issued, #1757 property reset
> operators, and #1758 Boolean implication and equivalence operators.
> I also uploaded a new proposal for #1683 and #1728 (still a draft).
> 
> Attached all here for convenience.
> 
> Best regards,
> ed
> 
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