Hi, I think that we should keep the inference in ordinary always blocks provided they satisfy certain rules. If people want to use it, they will conform to the restriction. If not, they can always use explicit clocks and disable iff. On always_ff it can follow what the description for always_ff indicates. ed > -----Original Message----- > From: owner-sv-ac@eda.org [mailto:owner-sv-ac@eda.org] On > Behalf Of Jonathan Bromley > Sent: Monday, March 12, 2007 5:30 AM > To: Bresticker, Shalom; sv-ac@eda-stds.org > Subject: RE: [sv-ac] Updated #1648: default disable > > > Why don't you need to alter any good existing RLT code? > > You need to change 'always' to 'always_ff'. > > yes, and NOTHING else; which, if you are planning to add > some assertions, is hardly a punitive overhead. > -- > Jonathan Bromley, Consultant > > DOULOS - Developing Design Know-how > VHDL * Verilog * SystemC * e * Perl * Tcl/Tk * Project Services > > Doulos Ltd. Church Hatch, 22 Market Place, Ringwood, > Hampshire, BH24 1AW, UK > Tel: +44 (0)1425 471223 Email: > jonathan.bromley@doulos.com > Fax: +44 (0)1425 471573 Web: > http://www.doulos.com > > The contents of this message may contain personal views which > are not the views of Doulos Ltd., unless specifically stated. > > -- > This message has been scanned for viruses and > dangerous content by MailScanner, and is > believed to be clean. > > > -- This message has been scanned for viruses and dangerous content by MailScanner, and is believed to be clean.Received on Mon Mar 12 06:06:55 2007
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