RE: [sv-ac] Updated #1648: default disable

From: Eduard Cerny <Eduard.Cerny_at_.....>
Date: Mon Mar 12 2007 - 06:06:32 PDT
Hi,

I think that we should keep the inference in ordinary always blocks
provided they satisfy certain rules. If people want to use it, they will
conform to the restriction. If not, they can always use explicit clocks
and disable iff.  On always_ff it can follow what the description for
always_ff indicates.

ed


> -----Original Message-----
> From: owner-sv-ac@eda.org [mailto:owner-sv-ac@eda.org] On 
> Behalf Of Jonathan Bromley
> Sent: Monday, March 12, 2007 5:30 AM
> To: Bresticker, Shalom; sv-ac@eda-stds.org
> Subject: RE: [sv-ac] Updated #1648: default disable
> 
> > Why don't you need to alter any good existing RLT code?
> > You need to change 'always' to 'always_ff'.
> 
> yes, and NOTHING else; which, if you are planning to add
> some assertions, is hardly a punitive overhead.
> -- 
> Jonathan Bromley, Consultant
> 
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Received on Mon Mar 12 06:06:55 2007

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