Re: [sv-ac] Updated #1648: default disable

But then even the current inference would not work. The user has to respect some methdology.
Ed

-----Original Message-----
From: Thomas.Thatcher@Sun.COM <Thomas.Thatcher@Sun.COM>
To: Bresticker, Shalom <shalom.bresticker@intel.com>
CC: Eduard Cerny <Eduard.Cerny@synopsys.COM>; sv-ac@eda-stds.org <sv-ac@eda-stds.org>
Sent: Fri Mar 09 12:59:26 2007
Subject: Re: [sv-ac] Updated #1648: default disable

Hi Shalom, Ed

Wow!  So that means that the following always block could be "synthesizable",
(at least according to a broad interpretation of Std 1364.1-2002), but the
current proposal would infer the wrong disable!

    always @(negedge nrst or posedge clk) begin
	if (!nrst) begin
	    q <= 1'b0;
	else begin
	    q <= d;
	    assert property (d == exp_data);
	end
    end


After thinking about this for a while, I believe the inference of asynchronous
disables should be based on the always block logic, not solely on the contents
of the timing control of the always block.  This would be more consistent with
section 17.13.5, which describes the inference of enable signals.

    "Another inference made from the context is the enabling condition for
    a property.  Such derivation takes place when a property is placed in
    and if..else or a case block."

Tom

Bresticker, Shalom wrote On 03/09/07 01:56,:
> It's not wrong.
> Synthesis tools do not require the clock to be the first event in the
> list.
> In fact, the next line after the one you quoted is:
> 
> "// Any sequence of edge events can be in event list."
> 
> Shalom
> 
> 
> 
>>One other interesting note:  I went to double check the multiple reset
>>conditions by calling up the 1364.1-2002 standard (Verilog RTL
>>Synthesis).
>>Here's what I read:  (Sec 5.2.2.1, p 9)
>>
>>    The always statement shall be of the form:
>>
>>	always @ (posedge <condA> or negedge <condB> or negedge <condC>
> 
> or
> 
>>...
>>		posedge <Clock>)
>>			^^^^^^^??????
>>Isn't that backwards?  The clock event should be the first event in
>>the list.
>>In fact all four examples on the next page have the clock as the first
>>event in the list.

-- 
------------------
Thomas J. Thatcher
Sun Microsystems
408-616-5589
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