RE: [sv-ac] Updated #1648: default disable

I suppose that in 1648 we could impose an order and define when
inference can be used, i.e., under which order of evet expressions. If
not then this inference should be scrapped. what do you say?
ed
 

> -----Original Message-----
> From: Bresticker, Shalom [mailto:shalom.bresticker@intel.com] 
> Sent: Friday, March 09, 2007 4:57 AM
> To: Thomas.Thatcher@Sun.COM; Eduard Cerny
> Cc: sv-ac@eda-stds.org
> Subject: RE: [sv-ac] Updated #1648: default disable
> 
> It's not wrong.
> Synthesis tools do not require the clock to be the first event in the
> list.
> In fact, the next line after the one you quoted is:
> 
> "// Any sequence of edge events can be in event list."
> 
> Shalom
> 
> 
> > One other interesting note:  I went to double check the 
> multiple reset
> > conditions by calling up the 1364.1-2002 standard (Verilog RTL
> > Synthesis).
> > Here's what I read:  (Sec 5.2.2.1, p 9)
> > 
> >     The always statement shall be of the form:
> > 
> > 	always @ (posedge <condA> or negedge <condB> or negedge <condC>
> or
> > ...
> > 		posedge <Clock>)
> > 			^^^^^^^??????
> > Isn't that backwards?  The clock event should be the first event in
> > the list.
> > In fact all four examples on the next page have the clock 
> as the first
> > event in the list.
> 

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