RE: [sv-ac] $past - number_of_ticks proposal

Why could it not be at least a constant_expression?

Shalom

> -----Original Message-----
> From: owner-sv-ac@server.eda.org [mailto:owner-sv-ac@server.eda.org]
> On Behalf Of Clifford E. Cummings
> Sent: Friday, March 09, 2007 9:34 AM
> To: sv-ac@server.eda.org
> Subject: [sv-ac] $past - number_of_ticks proposal
> 
> Hi, All -
> 
> A clarification question came up in one of my SystemVerilog classes
> regarding the $past number_of_ticks argument. A student questioned
> whether the argument could be an expression and I believe the answer
> is no, but LRM does not definitively make a precise definition. There
> is no BNF to describe the $past arguments.
> 
> I did a SVDB search on number_of_ticks and only found Mantis item
> 1591, which did not cover the topic.
> 
> Proposal (if my assumption is correct):
> 
> 17.7.3 Sampled value functions
> Bottom of page 247
> 
> WAS:
> number_of_ticks must be 1 or greater. If number_of_ticks is not
> specified, then it defaults to 1. $past returns the sampled value of
> the expression that was present number_of_ticks prior to the time of
> evaluation of $past. A clock tick is based on clocking_event. If the
> specified clock tick in the past is before the start of simulation,
> the returned value from the $past function is a value of X.
> 
> PROPOSED:
> number_of_ticks must be an integer constant of 1 or greater. If
> number_of_ticks is not specified, then it defaults to 1. $past
> returns the sampled value of the expression that was present
> number_of_ticks prior to the time of evaluation of $past. A clock
> tick is based on clocking_event. If the specified clock tick in the
> past is before the start of simulation, the returned value from the
> $past function is a value of X.
> 
> Regards - Cliff
> 
> 
> 
> ----------------------------------------------------
> Cliff Cummings - Sunburst Design, Inc.
> 14314 SW Allen Blvd., PMB 501, Beaverton, OR 97005
> Phone: 503-641-8446 / FAX: 503-641-8486
> cliffc@sunburst-design.com / www.sunburst-design.com
> Expert Verilog, SystemVerilog, Synthesis and Verification Training
> 
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