Hi John, I made the requested change and have uploaded the latest. It is attached for convenience. If my answers to your questions were satisfactory then it is ready for vote. I will not be able to attend the meeting today - I'll check the meeting notes for status. Lisa -----Original Message----- From: John Havlicek [mailto:john.havlicek@freescale.com] Sent: Tuesday, March 06, 2007 12:22 AM To: Lisa Piper Cc: sv-ac@eda-stds.org Subject: comments on 1722 Hi Lisa: I have read the proposal for 1722 and have the comments below. J.H. - Should the bind discussion be moved to Clause 19 as suggested by Jonathan Bromley? This could invite a change in the way the motivation is presented. - I understand the motivation of attaching verification code to design code without touching the design. However, I don't like the sentence SystemVerilog provides a bind construct that allows for instantiating a module, interface, or program block into design code without touching the design code. because it suggests that only design code targets are allowed. I prefer something like SystemVerilog provides a bind construct that is used to specify one or more instantiations of a module, interface, or program block without modifying the code of the target. - I see the text you pointed out: It shall be an error for a bind statement to bind a bind_instantiation underneath the scope of another bind_instantiation. Suppose I have module C that I bind. Is this saying that it is illegal to bind and instance module D to target scope C? If not, then are we saying that there are different capabilities for binding to target scope and target instance when multiple bindings are involved? -- This message has been scanned for viruses and dangerous content by MailScanner, and is believed to be clean.
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