Re: [sv-ac] call to vote on 1668

Hi Hillel:

Pushing the sampling to the previous clock will not be
semantically continuous with the singly-clocked case.  In 
other words, the multiply-clocked definition will not reduce 
to the singly-clocked definition in case all the clocks are the
same.

In my opinion that would be a mistake.

We should discuss this further.

J.H.

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> Thread-Topic: [sv-ac] call to vote on 1668
> Thread-Index: Acdc8XsKRfsWi5n6TMyz2158mAMTywAukyNQ
> From: "Miller Hillel-R53776" <r53776@freescale.com>
> Cc: <sv-ac@eda-stds.org>
> 
> John,
> 
> I am in favour of this proposal if it is updated to handle the sampling
> issue.
> 
> I am in favour of sampling the declaration assignments using the
> previous clocks, it does not make sense to syntactically look forward to
> know the clock.
> 
> I never knew the non-overlapping implication rewrite rule put the clock
> in "no mans land".  Can this be changed to keep the clock as ev0? What
> was the reasoning with the "no mans land" sampling clock change?
> 
> "and the rewrite for "|=3D>" would give
> 
>    @(ev0) r ##1 (@(1)1) |-> ((1,v=3De) |-> (@(ev1) q1 and @(ev2) q2))
>  "
> 
> Thanks
> 
> Hillel Miller>
> 
> 

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