RE: [sv-ac] 1722 Bind Clarifications

From: Jonathan Bromley <jonathan.bromley_at_.....>
Date: Thu Feb 22 2007 - 15:37:20 PST
> It is not quite clear why bind definition belongs to Clause 17 at all.

Agreed.

It's SystemVerilog's "stealth feature".

The discussion belongs with clause 19, Hierarchy.

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Received on Thu Feb 22 15:37:44 2007

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