Re: [sv-ac] 1547 review

Hi Shalom:

I am miserably confused both about the intent of the capability
of putting assertion items within clocking blocks and modports and 
about whether the various restrictions allow the intent to be
realized.

Regarding the sampling, there is the following language in 17.3:

   If a variable used in an assertion is a clocking block input
   variable, the variable must be sampled by the clocking block with
   #1step sampling. Any other type of sampling for the clocking block
   variable shall result in an error. The assertion using the clocking
   block variable shall not do its own sampling on the variable, but
   rather use the sampled value produced by the clocking block. This
   is explained in Clause 9.

I'm not sure what you get if you refer to both clocking block inputs
and outputs within an assertion.

J.H.

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> Thread-Topic: [sv-ac] 1547 review
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> From: "Bresticker, Shalom" <shalom.bresticker@intel.com>
> Cc: <sv-ac@eda-stds.org>
> X-OriginalArrivalTime: 22 Feb 2007 10:32:48.0122 (UTC) FILETIME=[CBEEA5A0:01C7566C]
> 
> I have no opinion on the issue, but as to why someone might want
> assertion constructs in a clocking block, Ed previously wrote:
> 
> "I could see a case where the user has a clocking block for specifying
> sampling and driving and wants to put assertions on the signals that are
> marked as input, output, ...=20
> BUT, I hope that it will not confuse the user that the assertions sample
> at 1step while the clocking block specifies some other sampling and
> driving offset."
> 
> Shalom
> 
> 
> > I think we need to review the way assertion constructs
> > can or cannot be put into clocking blocks, interfaces, and
> > modports.

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