RE: [sv-ac] 1722 Bind Clarifications

Hi Lisa,
 
Yes, that's simpler and better. Perhaps one could add the property stuff
as an example, by saying that assertion-based checkers encapsulated in
modules or interfaces can be thus bound non-intrusively to the design.
Or something like that.
 
ed


________________________________

	From: Lisa Piper [mailto:piper@cadence.com] 
	Sent: Friday, February 16, 2007 9:23 AM
	To: Eduard Cerny; sv-ac@eda-stds.org
	Subject: RE: [sv-ac] 1722 Bind Clarifications
	
	

	Hi Ed,

	 

	I agree. I was trying to avoid the overhaul, but ..  I have
issues with all the dashed items too (see the green text below):

	 

	To facilitate verification separate from design, it is possible
to specify properties and bind them to specific modules or instances.
The following are some goals of providing this feature:

	 

	- It allows verification engineers to verify with minimum
changes to the design code and files. (why minimum verses "no" changes
to the design code)

	- It allows a convenient mechanism to attach verification
Internet Protocol (IP) to a module or an instance.(technically this
needs to be reworded to include interface also)

	- No semantic changes to the assertions are introduced due to
this feature. It is equivalent to writing properties external to a
module, using hierarchical path names. (I prefer to think of it as being
instantiated, and again the properties must be wrapped in a module -
this may imply compilation unit scope)

	 

	With this feature, a user can bind a module, interface, or
program instance to a module or a module instance.

	 

	How about we change it to simply read:

	 

	It is often desired to keep verification code separate from the
design code.  SystemVerilog provides a bind construct that allows for
instantiating a module, interface, or program block into design code
without touching the design code. With this feature, a user can bind a
module, interface, or program instance to a module or a module instance.
An interface could also be bound to an interface or interface instance.

	 

	 

	
________________________________


	From: Eduard Cerny [mailto:Eduard.Cerny@synopsys.com] 
	Sent: Thursday, February 15, 2007 3:18 PM
	To: Lisa Piper; sv-ac@eda-stds.org
	Subject: RE: [sv-ac] 1722 Bind Clarifications

	 

	Hi,

	 

	reading the following text (in the LRM and the updated text)
makes me wonder:

	"To facilitate verification separate from design, it is possible
to specify properties and bind them to specific ..."

	 

	How does one specify "properties" to bind them? The only way is
to put them in verification statements and then a module, interface or
program and then bind. Isn't the sentence a bit misleading?

	 

	Regards,

	ed

	
	
	 

		
________________________________


		From: owner-sv-ac@eda.org [mailto:owner-sv-ac@eda.org]
On Behalf Of Lisa Piper
		Sent: Thursday, February 15, 2007 2:51 PM
		To: sv-ac@eda-stds.org
		Subject: [sv-ac] 1722 Bind Clarifications

		Hi all,

		 

		I have uploaded a revised version of this proposal.
While nothing significant in content has intentionally changed, the
format is very different so another review should be done.  I have
attached the new version for convenience.

		 

		Lisa

		
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