RE: [sv-ac] 1722 Bind Clarifications

Hi,
 
reading the following text (in the LRM and the updated text) makes me
wonder:
"To facilitate verification separate from design, it is possible to
specify properties and bind them to specific ..."
 
How does one specify "properties" to bind them? The only way is to put
them in verification statements and then a module, interface or program
and then bind. Isn't the sentence a bit misleading?
 
Regards,
ed

 

________________________________

	From: owner-sv-ac@eda.org [mailto:owner-sv-ac@eda.org] On Behalf
Of Lisa Piper
	Sent: Thursday, February 15, 2007 2:51 PM
	To: sv-ac@eda-stds.org
	Subject: [sv-ac] 1722 Bind Clarifications
	
	

	Hi all,

	 

	I have uploaded a revised version of this proposal.  While
nothing significant in content has intentionally changed, the format is
very different so another review should be done.  I have attached the
new version for convenience.

	 

	Lisa


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