RE: [sv-ac] issues with 1460

Hi all,

I updated the PDF file. Attached it here for convenience. Besides of the
typo fix, the changes are as follows:

Old:

When the property for the assume statement is evaluated to be true, the
pass statements of the action block are executed. Otherwise, the fail
statements of the action block are executed. For example:

property abc ( a , b , c ) ;
    disable iff ( c ) @(posedge clk) a |=> b ;
endproperty
env_prop : assume property ( abc ( req , gnt , rst ) ) ; else $error (
"Assumption failed." ) ;

New:

When the property for the assume statement is evaluated to be true, the
pass statements of the action block are executed. If it evaluates to
false, the fail statements of the action block are executed. For
example:

property abc(a, b, c) ;
    disable iff (c) @(posedge clk) a |=> b ;
endproperty
env_prop :
assume property (abc(req , gnt , rst) ) ; else $error( "Assumption
failed." ) ;

If the property has a disabled evaluation, neither pass nor fail
statements of the action block are executed.

-----Original Message-----
From: owner-sv-ac@server.eda.org [mailto:owner-sv-ac@server.eda.org] On
Behalf Of John Havlicek
Sent: Wednesday, February 14, 2007 10:47 PM
To: sv-ac@server.eda-stds.org
Cc: Brad.Pierce@synopsys.com
Subject: [sv-ac] issues with 1460

All:

Brad Pierce has added a bugnote to 1460 pointing out that the open
parenthesis in the change descriptions for Syntax 17-6 is in the wrong
place.  I agree with him -- the parentheses should enclose
property_spec only, as we have currently in the LRM.

On reviewing this I noticed another problem.  This proposal is not
consistent with the changes in 0805.  Disabled attempts should result
in neither the pass nor the fail statements being executing.

I added a bugnote for the second problem, but that required me to
reopen the issue and put its status as "feedback".

Dmitry -- Can you update the proposal so that we can address these
minor changes in the next meeting?

Best regards,

John H.

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