RE: [sv-ac] reminder to vote on mantis 1550

Hi John,

please see below.

ed 

> -----Original Message-----
> From: John Havlicek [mailto:john.havlicek@freescale.com] 
> Sent: Friday, January 26, 2007 10:32 AM
> To: Eduard.Cerny@synopsys.COM
> Cc: john.havlicek@freescale.com; Eduard.Cerny@synopsys.COM; 
> sv-ac@eda-stds.org
> Subject: Re: [sv-ac] reminder to vote on mantis 1550
> 
> Hi Ed:
> 
> I think we should not be clarifying Section 9.  I think we
> should ask whoever is responsible for Section 9 to do the
> clarification, although we can send them suggestions.
> 
> Do you agree that declaration assignments are executed as
> part of
> 
>    initialize the values of all nets and variables

That is not implied and should be added. We could add that in relaten to
$sampled, but it affects sampling in clocking blocks and assertions. So
it should go to SV-BC? But, it may do no harm to repeat that in 1550 for
$sampled and the other functions.


> 
> ?  If not, then this certainly needs clarification.
> 
> Do we all agree that the initial blocks are not a part
> of this and that they get scheduled in the active region
> of the time 0 slot?

I do.

> 
> J.H.
> 
> > X-MimeOLE: Produced By Microsoft Exchange V6.5
> > Content-class: urn:content-classes:message
> > Date: Fri, 26 Jan 2007 07:22:32 -0800
> > Thread-Topic: [sv-ac] reminder to vote on mantis 1550
> > Thread-Index: AcdBW9xQw8waBr6YTHqAutCt1fwOeAAAaMcg
> > From: "Eduard Cerny" <Eduard.Cerny@synopsys.com>
> > Cc: <sv-ac@eda-stds.org>
> > X-OriginalArrivalTime: 26 Jan 2007 15:22:33.0619 (UTC) 
> FILETIME=[CD57B630:01C7415D]
> > 
> > Hi John,
> > 
> > I agree that this is what should happen, but as you say 
> yourself, it is
> > not stated in the algorithm. Should we add that there? Or 
> in 1550 just
> > for the sampled value fncts? I'd still like to add that 
> that result of
> > initializationa nd evaluation sets values that can be thought of as
> > being valid from -oo till 0-.
> > 
> > ed
> > 
> >  =20
> > 
> > > -----Original Message-----
> > > From: John Havlicek [mailto:john.havlicek@freescale.com]=20
> > > Sent: Friday, January 26, 2007 10:08 AM
> > > To: Eduard.Cerny@synopsys.COM
> > > Cc: john.havlicek@freescale.com; Eduard.Cerny@synopsys.COM;=20
> > > sv-ac@eda-stds.org
> > > Subject: Re: [sv-ac] reminder to vote on mantis 1550
> > >=20
> > > Hi Ed:
> > >=20
> > > I never said anything got scheduled into the preponed region.
> > >=20
> > > Look at the scheduling algorithm.  The step
> > >=20
> > >   initialize the values of all nets and variables
> > >=20
> > > executes before the execution of the time 0 slot begins.  My
> > > interpretation is that this step includes execution of the=20
> > > declaration assignments.
> > >=20
> > > The value of an expression should be readable in the=20
> > > preponed region.  What I am saying is that if an expression
> > > is read (or sampled) in the preponed region of the time 0 slot,
> > > then it should see the effects of the=20
> > >=20
> > >   initialize the values of all nets and variables
> > >=20
> > > In other words, the declaration assignments are reflected in=20
> > > the preponed values in the time 0 slot.
> > >=20
> > > Do you disagree?
> > >=20
> > > J.H.
> > >=20
> > >=20
> 

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