RE: [sv-ac] reminder to vote on mantis 1550

It would break backward compatibility. Also, all variables are set by
default to the values indicated in 1550, why this should be different?
 
ed


________________________________

	From: Miller Hillel-R53776 [mailto:r53776@freescale.com] 
	Sent: Wednesday, January 24, 2007 1:31 PM
	To: Eduard Cerny; Havlicek John-r8aaau; sv-ac@eda-stds.org
	Subject: RE: [sv-ac] reminder to vote on mantis 1550
	
	
	Still what is wrong with the proposal to use the value after
initialization at time 0? Where does this break consistency?

________________________________

	From: Eduard Cerny [mailto:Eduard.Cerny@synopsys.com] 
	Sent: Wednesday, January 24, 2007 8:27 PM
	To: Miller Hillel-R53776; Eduard Cerny; Havlicek John-r8aaau;
sv-ac@eda-stds.org
	Subject: RE: [sv-ac] reminder to vote on mantis 1550
	
	
	Hi Hillel,
	 
	apart from the uesr initialization, what is really the problem
with the current definition? Yes, it can happen when there is a clocking
event at time 0, or if you have $past with longer number of clocks to go
back, etc.
	 
	Best regards,
	ed
	 
	PS the forced initialization can be a feature of a tool, not the
LRM.
	 


________________________________

		From: Miller Hillel-R53776 [mailto:r53776@freescale.com]

		Sent: Wednesday, January 24, 2007 1:14 PM
		To: Eduard Cerny; Havlicek John-r8aaau;
sv-ac@eda-stds.org
		Subject: RE: [sv-ac] reminder to vote on mantis 1550
		
		
		Ed,
		 
		What $ functions use $sampled values which are to be
before time 0?
		 
		Does this happen when there is a "clocking event" at
time zero? 
		 
		Why can't we take the route of using the values after
initialization as the $sampled value in the first preponed region at
time 0? What does this break?
		 
		There also needs to be away to allow the user to control
the initialization of the $functions at time Zero. This could be needed
if a counter example is produced by a formal tool that needs to be
replayed in simulation. If the $sampled at the first preponed region is
from the time 0 initilization stage then this is doable.
		 
		Thanks
		Hillel
		 
		 
		 
________________________________

		From: Eduard Cerny [mailto:Eduard.Cerny@synopsys.com] 
		Sent: Wednesday, January 24, 2007 4:31 PM
		To: Miller Hillel-R53776; Havlicek John-r8aaau;
sv-ac@eda-stds.org
		Subject: RE: [sv-ac] reminder to vote on mantis 1550
		
		
		Hello Hillel,
		But the functions use $sampled values which are to be
before time 0. Hence the initialization to the default value of the
type. What else would you suggest?ed
		 


________________________________

			From: owner-sv-ac@eda.org
[mailto:owner-sv-ac@eda.org] On Behalf Of Miller Hillel-R53776
			Sent: Wednesday, January 24, 2007 8:53 AM
			To: Havlicek John-r8aaau; sv-ac@eda-stds.org
			Subject: RE: [sv-ac] reminder to vote on mantis
1550
			
			

			Hi,

			I vote no even though I am not elligible. The
reason is that it is not clear what the intialized values are of the $
functions.

			The current schedular code shows an
initialization process, before going into the first preponed area (see
below). This means that the initial value of an expression is determined
by its initilization at time slot 0 and not by its default type value as
specified in the proposal.

			execute_simulation {

			T = 0;

			initialize the values of all nets and variables;

			schedule all initialization events into time 0
slot;

			while (some time slot is nonempty) {

			move to the next future nonempty time slot and
set T; 

			execute_time_slot (T);

			}

			}

			Hillel Miller>


			-----Original Message-----

			From: owner-sv-ac@eda.org
[mailto:owner-sv-ac@eda.org <mailto:owner-sv-ac@eda.org> ] On Behalf Of
John Havlicek

			Sent: Tuesday, January 23, 2007 9:35 PM

			To: sv-ac@eda-stds.org

			Subject: [sv-ac] reminder to vote on mantis 1550

			All:

			This is a reminder that a vote on mantis 1550
was called in today's meeting.  Please see the details below.

			J.H.

			Ballot on Mantis 1550

			- Called on 2007-01-23, final ballots due by
23:59 PST on 2007-01-30.

			- Voting eligibility for this ballot is shown
below.

			- If you are eligible to vote then please do, as
80% participation

			  in ballots is required to maintain
eligibility.

			 n[-------xxx------] Shalom Bresticker (Intel)
v[xxxxxxxxxxxxx-xx] Doron Bustan (Freescale)

			 v[xxxxxxxxxxxxxx-x] Eduard Cerny (Synopsys)    

			 n[---x-x-xxx-x---x] Surrendra Dudani (Synopsys)
v[x-xxx-xxx-------] Yaniv Fais (Freescale)  n[---x------x-----] Faisal
Haque (Cisco)  t[xxxxxxxxxxxxxxxx] John Havlicek (Freescale - Chair)
v[xxxxxxxxxxxx-xxx] Dmitry Korchemny (Intel - Co-Chair)
n[---------xx-xxxx] Manisha Kulshrestha (Mentor Graphics)
v[xx-------x-xx-x-] Jiang Long (Mentor Graphics)  n[x--xx-xxxxxxx-x-]
Hillel Miller (Freescale)  n[-----xx-xxx-----] Don Mills (Microchip)
v[xxxxxx-xxxxxxxxx] Lisa Piper (Cadence)  v[xxx-xx----------] Tej Singh
(Mentor Graphics)  n[------xx-x------] Stu Sutherland (Sutherland HDL)
v[xxxxxxxxxxxxxxxx] Bassam Tabbara (Synopsys)  n[x...............] Tom
Thatcher (Sun Microsystems)

			   |--------------- attendance on 2007-01-23

			 |----------------- voting eligibility for this
ballot

			|------------------ email ballots received

			        Legend:

			                x = attended

			                - = missed

			                r = represented

			                . = not yet a member

			                v = valid voter (2 out of last
3)

			                n = not valid voter

			                t = chair eligible to vote only
to make or break a tie

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