Re: [sv-ac] example

thanks Ed,

I changed it.

Doron

Eduard Cerny wrote:

>Hi Doron,
>
>I will look at the example in more detail, but just a cursory look:
>the declaration
>bit a_D1 = $past(a,,,posedge clk);
>will only assign value at time 0 since it is an initializer statement
>only. If you want to have it assigned continuously,
>use
>bit a_D1;
>assign a_D1 = $past(a,,,posedge clk);
>
>Best regards,
>ed
>
>PS I have the alternate definition, using eval that depends on the
>calling context, however, the needed change in SV scheduling is still
>only being discussed, not logged, in SV-EC. So i am waiting to see how
>that will  evolve first.
>
>
>  
>
>>-----Original Message-----
>>From: owner-sv-ac@eda.org [mailto:owner-sv-ac@eda.org] On 
>>Behalf Of Doron Bustan
>>Sent: Wednesday, November 29, 2006 2:41 PM
>>To: sv-ac@eda.org
>>Subject: [sv-ac] example
>>
>>All
>>
>>attached an example that demonstrates a gap between updating 
>>a variable 
>>using NBA
>>and updating it using $past that being updated by it self in the 
>>postpond region.
>>
>>Doron
>>    
>>
>
>  
>


This example demonstrates inconsistency of using NBA and $past 
to update variables.

First look at an module that use NBA to update a_D1
---------------------------------------------------
module stam(
input clk,
input a,
input b,
output bit out1
);

bit a_D1;

bit c1;

always @(posedge clk)
  a_D1 <= a;

always @(a_D1)
    c1 = (a_D1) ? 1 : 0;

always @(c1)
   if (c1) 
      out1 = b;

endmodule
---------------------------------------------------

In The following scenario out1 remains 0 at all time steps:

|------------------------------------------------------------------------------------------------
|signal/timestep |  0   |   1   |   2   |   3   |   4   |   5   |   6   |   7   |   8   |   9   |
|================================================================================================
|clk             |  0   |   1   |   1   |   0   |   0   |   1   |   1   |   0   |   0   |   1   |
|------------------------------------------------------------------------------------------------
|a               |  0   |   0   |   1   |   1   |   1   |   1   |   1   |   1   |   1   |   1   |
|------------------------------------------------------------------------------------------------
|b               |  1   |   1   |   0   |   0   |   0   |   0   |   1   |   1   |   1   |   1   |
|------------------------------------------------------------------------------------------------
|a_D1            |  0   |   0   |   0   |   0   |   0   |   1   |   1   |   1   |   1   |   1   |
|------------------------------------------------------------------------------------------------
|c1              |  0   |   0   |   0   |   0   |   0   |   1   |   1   |   1   |   1   |   1   |
|------------------------------------------------------------------------------------------------
|out1            |  0   |   0   |   0   |   0   |   0   |   0   |   0   |   0   |   0   |   0   |
|------------------------------------------------------------------------------------------------





 however if we use $past to update a_D1 as follows:
---------------------------------------------------
module stam(
input clk,
input a,
input b,
output bit  out1
);

bit a_D1;
assign a_D1 = $past(a,,,posedge clk);

bit c1;

always @(a_D1)
    c1 = (a_D1) ? 1 : 0;

always @(c1)
   if (c1) 
      out1 = b;

endmodule
---------------------------------------------------

then $past(a,,,clk) is being updated in the postpond region,


I am not sure where  a_D1 = $past(a,,,clk) is being
scheduled, but out1 = b is being scheduled in the active region of the the next time step. 
The result for the same scenario is:

|------------------------------------------------------------------------------------------------
|signal/timestep |  0   |   1   |   2   |   3   |   4   |   5   |   6   |   7   |   8   |   9   |
|================================================================================================
|clk             |  0   |   1   |   1   |   0   |   0   |   1   |   1   |   0   |   0   |   1   |
|------------------------------------------------------------------------------------------------
|a               |  0   |   0   |   1   |   1   |   1   |   1   |   1   |   1   |   1   |   1   |
|------------------------------------------------------------------------------------------------
|b               |  1   |   1   |   0   |   0   |   0   |   0   |   1   |   1   |   1   |   1   |
|------------------------------------------------------------------------------------------------
|a_D1            |  0   |   0   |   0   |   0   |   0   |   1?  |   1   |   1   |   1   |   1   |
|------------------------------------------------------------------------------------------------
|c1              |  0   |   0   |   0   |   0   |   0   |   0   |   1   |   1   |   1   |   1   |
|------------------------------------------------------------------------------------------------
|out1            |  0   |   0   |   0   |   0   |   0   |   0   |   1   |   1   |   1   |   1   |
|------------------------------------------------------------------------------------------------


Note that out1 turn high at cycle 6.