[sv-ac] blocking assignments

Just to make sure that I don't miss something important...

In the example:

always @(posedge clk) begin
                if (cond) begin
                     a = b;
                     assert (a == c) ;
                     b = c;
               end
end

the assertion is being evaluated at most once in every "clk" cycle.


I think that we need more than one always block to cause the assertion to
execute more than once, something like:

always @(b) begin
               if (cond) begin
                     a = b;
                     assert (a == c) ;
               end
end

always @(c) begin
            b = c;
end

this will cause the assert to possibly fire twice at the same time step 
without
exiting the active region. We should also consider the following case:


always @(b) begin
               if (cond) begin
                     a = b;
                     assert (a == c) ;
               end
end

always @(c) begin
            b <= c;
end

Here the assert is being triggered twice, but the simulator goes to the NBA
region between the two triggers.


is this right?

Doron