RE: [sv-ac] question on bind

From: Faisal Haque \(fhaque\) <fhaque_at_.....>
Date: Thu Oct 19 2006 - 12:16:35 PDT
Lisa I think it might be useful to pass some testbench related data to
the assertions.
-Faisal
 


________________________________

	From: owner-sv-ac@eda.org [mailto:owner-sv-ac@eda.org] On Behalf
Of Lisa Piper
	Sent: Thursday, October 19, 2006 10:39 AM
	To: sv-ac@eda-stds.org
	Subject: [sv-ac] question on bind
	
	

	Hi all,

	 

	I have noticed some inconsistencies in Section 17.15 text and
the BNF in A.1.4 that relate to bind.  The text after the BNF states
that "Possible target scopes include module, program, and interface
declarations"   but the BNF only shows modules and interfaces. 

	 

	Is there a need to be able to have a program as the bind target
scope?  If so, can you give me an example?

	 

	Lisa

	 
Received on Thu Oct 19 12:16:59 2006

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