[sv-ac] expect statement inside function

I have a quary regarding an 'expect' statement  inside function.
According to v2k LRM 1364_2001  LRM section:
                                                  10.3.4 Function rules
                                                          a) A function 
definition shall not contain any time-controlled statements that is,any 
statements introduced with #,@,or wait .

But IEEE SV LRM says that:
            A.2.6 (BNF)
                   A.2.6 Function declarations
                               function_body_declaration ::=
                                                           { 
function_statement_or_null }
                               function_statement_or_null ::=
                                                            
function_statement
                                  function_statement ::= statement
                               statement ::= [ block_identifier : ] { 
attribute_instance } statement_item
                                  statement_item ::= | 
expect_property_statement
                      A.2.10    expect_property_statement ::=
                                                       expect ( 
property_spec ) action_block

So, from SV LRM it is clear that we can use 'expect' inside function, In 
IEEE SV LRM section: 17.16, says that "The expect statement can be 
incorporated in any procedural code, including tasks or class methods."
I have an example where I use 'expect' statement as :

module expect9 ( clk,  reset,  out );
    input clk;
    input reset;
    output[7:0] out;
    wire clk;
    wire reset;
    reg[7:0] out;
    always @( posedge clk or posedge reset )
      begin
           if( reset == 1'b1 )
           out <= 0;
           else
               out <= out + 1;
      end

sequence seq;
@(posedge clk) out[0] ##1 !out[0] ##2 (out[2])[*4];
 endsequence

 property p1;
@(posedge clk)
reset ##1 !reset |=> seq ##1 (!out[6])[*2] ;
 endproperty

function reg assert_func (input bit clk);
expect (p1)
   begin
     $display(" EXPECT STATMENT HOLDs INSIDE THE FUNCTION");
     return 0;
   end
 else
   begin
    $display(" EXPECT STATMENT DOES'NT HOLDs");
    return 1;
   end
endfunction

 always@(posedge clk)
  begin
   reg r;
   r = assert_func(clk);
    end
endmodule

 function does not allow any time control expression, so how can I use 
'expect' statement inside function?