RE: [sv-ac] IEEE 1800 SV-AC - minutes of meeting on 10/03/2006

Ed I attended todays meeting. 

Some comments:
- Adding the explicit pass by reference, with keyword 'ref''  does not
hurt backward compatibility. 
- To maintain backward compatibilty for pass by value I propose adding a
keyword to the SV language that would explicity declare a formal
argument to be assigned using (pbv) pass by value (e.g. pbv var1).
- ref is different to substituation in a couple of ways
-- type checking. I think only the number of bits need to be the same. I
am not sure this is real type checking.
-- bit selection cannot always be done on a substituted variable and may
give different results to pass by reference.
   For example:

   sequence a(a1)
      a1[1] ##1 a2;
   endsequence

   in substitution the instantiation

   a(e1 && e2) 

  is different to

   a(e1 && e2) when passing by reference.
- I recommend not expanding the capabilities of passing sequences and
properties and to stop from encouraging it. We most probably can get
equivalent capabilities with Dimitry's proposals later on (Dimitry
please comment). This approach is not natural at the functional level
and it does not meet the essence of the SystemVerilog language. For
example a task cannot have a task activation as a actual parameter. 


   

Hillel Miller


-----Original Message-----
From: owner-sv-ac@eda.org [mailto:owner-sv-ac@eda.org] On Behalf Of
Eduard Cerny
Sent: Tuesday, October 03, 2006 8:06 PM
To: sv-ac@eda.org
Subject: [sv-ac] IEEE 1800 SV-AC - minutes of meeting on 10/03/2006

Please find attached the minutes of today's meeting. Let me know if
corrections are required.

ed