RE: [sv-ac] question on 966

In view of Brad's comment, I guess the example would have to split the
if expression into two if's.

ed


> -----Original Message-----
> From: owner-sv-ac@eda-stds.org 
> [mailto:owner-sv-ac@eda-stds.org] On Behalf Of Brad Pierce
> Sent: Monday, July 10, 2006 5:04 PM
> To: sv-ac@eda-stds.org
> Subject: Re: [sv-ac] question on 966
> 
> Short-circuiting of expressions is optional in Verilog, not 
> mandatory.  
> 
>    http://www.boyd.com/1364_btf/report/full_pr/449.html
> 
> And the evaluation order for operands is unspecified.
> 
> -- Brad
> 
> -----Original Message-----
> From: owner-sv-ac@eda-stds.org [mailto:owner-sv-ac@eda-stds.org] On
> Behalf Of John Havlicek
> Sent: Monday, July 10, 2006 1:58 PM
> To: eduard.cerny@synopsys.COM
> Cc: sv-ac@eda-stds.org
> Subject: [sv-ac] question on 966
> 
> Ed:
> 
> I have a question about the restriction that a
> parameter to which $ is assigned not be used in 
> any expression.
> 
> In the example you have:
> 
>    generate
>       if (!$isunbounded(max_quiet) && (max_quiet == 0)) begin
>            ...
>       end
>       else begin
>            ...
>       end
>       ...
>    endgenerate
> 
> Is this really consistent with the restriction?  It looks to 
> me as though
> 
>    !$isunbounded(max_quiet) && (max_quiet == 0)
> 
> is one big expression (the condition of the "if").  Also, are there
> rules about early exit of the expression evaluation that are in force
> here so that if max_quiet is $, then you don't test whether $ == 0?
> 
> Best regards,
> 
> John H.
> 
>