RE: [sv-ac] formal types proposal

Hi Adam, please see my earlier email for both counts. On the latter,
again when the types are defined how to cast from/to would be addressed.

Thx.
-Bassam.

-----Original Message-----
From: Adam Krolnik [mailto:krolnik@lsil.com] 
Sent: Thursday, June 29, 2006 12:39 PM
To: Bassam Tabbara
Cc: Lisa Piper; sv-ac@verilog.org
Subject: Re: [sv-ac] formal types proposal



Hello all;

Is there a need for this?

o void: used when there are no data type restrictions, meaning that any
type is acceptible. The implicit type (that of the declaration of the
argument) is used for any semantic checks.  This is equivalent to
listing the argument prior to any typed arguments.

Can a sequence or property instance be used in place of a signal or
expression?
Can a signal or expression be used in place of a sequence or property
instance?
Or are there problems that prevent any type from being used?

Examples may help showing this in the LRM.

    Thanks.
-- 
     Soli Deo Gloria
     Adam Krolnik
     ZSP Verification Mgr.
     LSI Logic Corp.
     Plano TX. 75074
     Co-author "Assertion-Based Design"